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Josep Torrellas
Results: 154

#	Item
91	AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection -Abdullah Muzahid, Norimasa Otsuki, Josep Torrellas University of Illinois at Urbana-Champaign Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-24 12:36:17 Data management Data Concurrency Linearizability Lock Struct Atomicity Thread Software bug Concurrency control Transaction processing Computing
92	CAVA: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses LUIS CEZE, KARIN STRAUSS, JAMES TUCK, and JOSEP TORRELLAS University of Illinois at Urbana–Champaign and JOSE RENAU Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 00:10:17 Central processing unit Computer memory Runahead Cache CPU cache Branch predictor Microarchitecture Memory hierarchy Speculative execution Computer architecture Computer hardware Computer engineering
93	Replay Debugging: Leveraging Record and Replay for Program Debugging Nima Honarmand and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu/ Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-06-21 19:14:59 LLVM Clang Debugging D Printf format string Debuggers Software Computing Compilers
94	SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas CESR, NC State University [removed] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-23 23:23:55 Cryptography Debugging C Software bug Software testing Digital signature Computing Software engineering Computer programming
95	Colorama: Architectural Support for DataCentric Synchronization Luis Ceze, Pablo Montesinos, Christoph von Praun, Josep Torrellas PHJVTH NYV\W Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-24 11:54:30 Lock Palette Concurrency control Critical section Computing
96	AccMon: Automatically Detecting Memory-related Bugs via Program Counter-based Invariants ∗ Pin Zhou, Wei Liu, Long Fei† , Shan Lu, Feng Qin, Yuanyuan Zhou, Samuel Midkiff† and Josep Torrellas † Department of Comp Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2004-10-14 13:14:39 Software bugs Memory management Garbage collection Memory leak C dynamic memory allocation C Pointer Debugging Lookup table Computing Software engineering Computer programming
97	EVAL: Utilizing Processors with Variation-Induced Timing Errors∗ Smruti Sarangi, Brian Greskamp, Abhishek Tiwari, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iac Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-09-13 00:20:01 Computer architecture Microprocessors Central processing unit Digital signal processing Fuzzy control system Multi-core processor Control system CPU cache Control theory Computer hardware Computing Control engineering
98	Lessons Learned During the Development of the CapoOne Deterministic Multiprocessor Replay System Pablo Montesinos, Matthew Hicks, Wonsun Ahn, Samuel T. King and Josep Torrellas Department of Computer Science University o Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-23 17:56:46 Human behavior Motivation VisIt Behavior Application software Vladimiro Montesinos Software Cognition Experimental psychology
99	ReCycle: Pipeline Adaptation to Tolerate Process Variation∗ Abhishek Tiwari, Smruti R. Sarangi and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2007-04-11 01:31:00 Electronic engineering Central processing unit Pipeline Hazard Clock distribution network Clock skew Alpha 21264 CPU cache Computer architecture Computer hardware Clock signal

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